1. Field of the Invention
The present invention relates to a semiconductor memory device and method of operating the same, and more specifically to a semiconductor memory device having large number of input pins to receive external address signals and operating method thereof.
2. Description of the Background Art
Memory capacities of semiconductor memory devices, especially of DRAMs (Dynamic Random Access Memories) have been further increased recently. As the capacity is increased, chip area of a DRAM has come to be larger and larger, and the bit length of an address signal for specifying a memory cell to which data is to be written or from which data is to be read becomes longer and longer.
Generally, a DRAM having large storage capacity has a memory cell array divided into a plurality of blocks. FIG. 6 is a schematic block diagram showing the whole structure of a conventional DRAM having large capacity. In the example of FIG. 6, the memory cell array is divided into two blocks.
The structure and operation of the conventional DRAM having large capacity will be described with reference to FIG. 6.
Each of the memory cell array blocks 2a and 2b includes a plurality of memory cells MC arranged in a matrix of a plurality of rows and a plurality of columns, a plurality of word lines WL provided corresponding to the plurality of rows, and a plurality of bits lines BL1, BL2 provided corresponding to the plurality of columns.
A memory cell MC connected to one of the adjacent two bit lines BL1 and BL2 and a memory cell MC connected to the other one of the bit lines are connected to different word lines WL. The adjacent two bit lines BL1 and BL2 constitute one bit line pair BL.
Column decoders 24a and 24b, row decoders 25a and 25b, and sense amplifier.multidot.IO line circuits: 26a, 26b are provided corresponding to memory cell array blocks 2a and 2b, respectively.
A column predecoder 6 and a column address buffer 21 are provided commonly corresponding to the column decoders 24a and 24b.
Similarly, a row predecoder 4 and a row address buffer 3 are provided commonly corresponding to the row decoders 25a and 25b.
Address signals Aa, Ab and Ac externally applied to address input pads 10a, 10b and 10c are applied to each of the column address buffer 21 and the row address buffer 3.
Although three pads are shown as representing address input pads, actually a larger number of pads are provided as address input pads in a DRAM 1 having large capacity. For example, at least 11 address input pads are provided on a DRAM chip having the capacity of 4M. The address input pads receive the data of respective bits of the external address signal in parallel (multiple address input method).
The row address buffer 3 and the column address buffer 21 are controlled by a row address strobe signal/RAS and a column address strobe signal/CAS which are external control signals. In the specification "/" added before reference characters representing signals indicates that the signal is a low active signaL.
A control signal input pad 22 and a buffer 28 are provided for supplying external row address strobe signal/RAS to the row address buffer 3. Similarly, a control signal input pad 23 and a buffer 29 are provided for supplying an external column address strobe signal/CAS to the column address buffer 21.
The RAS buffer 28 buffers the row address strobe signal/RAS externally applied to the pad 22 and it applies the buffered signal to the row address buffer 3. The output signal from the RAS buffer 28 is hereinafter referred to as an internal row address strobe signal int/RAS.
Similarly, the CAS buffer 29 buffers the column address strobe signal/CAS externally applied to the pad 23 and it applies the buffered signal to the column address buffer 21. The output signal from the CAS buffer 29 will be hereinafter referred to as the internal column address strobe signal int/CAS.
The column address buffer 21 buffers the external address signals Aa-Ac from address input pads 10a-10c and supplies the buffered signals to the column predecoder 6 and an ATD (Address Transition Detector) circuit 7 while the internal column address strobe signal int/CAS from the buffer 29 is at a low level. The signal applied from the column address buffer 21 to the column predecoder 6 and to the ATD circuit 7 will be hereinafter referred to as an internal column address signal intAcl.
Meanwhile, the row address buffer 3 takes and temporarily stores external address signals Aa-Ac from address input pads 10a-10c in response to the fall of the internal row address strobe signal int/RAS from the buffer 29.
The signals stored in the row address buffer 3 are applied to a row predecoder 4. In the following description, a signal applied from the row address buffer 3 to the row predecoder 4 will be referred to as an internal row address signal intArw.
The column address buffer 21 includes a plurality of buffer circuits 210 provided corresponding to all address input pads 10a-10c. Each buffer circuit 210 operates while the internal column address strobe signal int/CAS is at the low level so that the external address signal from the corresponding address input pad is buffered and applied to the column predecoder 6 and the ATD circuit 7.
Similarly, the row address buffer 3 includes a plurality of buffer circuits 300 provided corresponding to all address input pads 10a-10c. Each buffer circuit 300 takes and temporarily stores the external address signal from the corresponding address input pad in response to the fall of the internal row address strobe signal int/RAS. The signal stored in each buffer circuit 300 is applied to the row predecoder 4.
The column predecoder 6 decodes the internal column address signal intAcl from the column address buffer 21 and applies the decoded signal to column decoders 24a and 24b.
The row predecoder 4 decodes the internal row address signal intArw from the row address buffer 3 and applies the decoded signal to the row decoders 25a and 25b.
The column decoder 24a further decodes the signal which has been decoded by the column predecoder 6, and to electrically connect only one corresponding pair of the bit line pairs BL in the memory cell array block 2a to the sense amplifier.multidot.IO line 26a.
Similarly, column decoder 24b further decodes the signal which has been decoded by the column predecoder 6, to electrically connect only one corresponding pair of the bit line pairs BL in the memory cell array block 2b to the sense amplifier.multidot.IO line 26b.
Row decoder 25a further decodes the signal from the row predecoder 4 to activate only one corresponding word line WL in the memory cell array 2a.
Similarly, the row decoder 25b further decodes the signal from the row predecoder 4 to activate only one corresponding word line WL in the memory cell array block 2b.
Writing and reading data to and from each memory cell MC can be carried out only when the word line WL connected to that memory cell is active.
Corresponding to the data stored in each memory cell MC connected to the word line WL which is active, the potential of the bit line BL1 or BL2 connected to the memory cell changes slightly. Consequently, there is generated a slight potential difference between the bit lines BL1 and BL2 constituting each bit line pair BL. In data reading, the sense amplifier.multidot.IO line circuit amplifies this slight potential difference and applies the amplified difference to an input/output circuit 27.
In data writing, sense amplifier.multidot.IO line circuit operates to force the potential of the bit line BL1 and the potential of the bit line BL2 which constitute a pair to complementary potentials corresponding to the data signal from the input/output circuit 27. The data stored in each memory cell MC connected to the word line WL which is active is rewritten by the data corresponding to the potential of the bit line BL1 or BL2 connected to that memory cell after the potentials are forced in such manner.
The input/output circuit 27 externally applies the output signals from sense amplifier.multidot.IO line circuits 26a and 26b as read data Dout through pads, not shown, in data reading. In data writing, the input/output circuit 27 supplies the data signal Din externally applied to the pads to the sense amplifier.multidot.IO line circuits 26a and 26b.
In data reading and data writing, row decoders 25a and 25b activate only one word line WL in the corresponding memory cell array blocks 2a and 2b, respectively, and each of the column decoders 24a and 24b electrically connects only one set of bit line pair BL in the corresponding memory cell array block 2a or 2b to the corresponding sense amplifier.multidot.IO line circuits 26a or 26b. Therefore, in data reading, data stored in one memory cell MC connected to the active word line WL and to either bit line BL1 or BL2 constituting the bit line pair BL electrically connected to the sense amplifier.multidot.IO line circuits 26a and 26b is externally read in each of the memory cell arrays 2a and 2b, respectively through the input/output circuit 27.
In data writing, external data is written to only one memory cell connected to the active word line WL and to either the bit line BL1 or BL2 constituting the bit line pair BL electrically connected to each of the sense amplifier.multidot.IO line circuits 26a and 26b, in each of the memory cell array blocks 2a and 2b, respectively through the input/output circuit 27. As to which word line WL is to be rendered active and which bit line pair BL is to be electrically connected to the sense amplifier.multidot.IO line circuits 26a and 26b, in each of the memory cell array blocks 2a and 2b it is determined dependent on the internal row address signal intArw from the row address buffer 3 and the internal column address signal intAcl from the column address buffer 21. Therefore, in each of the memory cell array blocks 2a and 2b, data is written to or read from a memory cell MC arranged at an intersection of a row designated by the external address signals Aa-Ac of the address input pads 10a-10c at the fall of the internal row address strobe signal int/RAS and a column designated by the external address signals Aa-Ac applied to the address input pads 10a-10c while the internal column address strobe signal int/CAS is at the low level.
The data stored in the DR extinguishes as time passes while the power is on. Therefore, it is necessary to prevent extinction of the data in the memory cell by rewriting the data same as the stored data in the memory cell MC at a timing earlier than the disappearance of the data stored in the memory cell MC. Such rewriting of data is called refreshing of data.
The internal address counter 5 successively generates address signals designating all rows of memory cells in each of the memory cell array blocks 2a and 2b and supplies these signals to the row address buffer 3.
The internal address counter 5 is provided for rewriting data in a prescribed period to each memory cell MC for refreshing data.
More specifically, the internal address counter 5 includes counters 500 provided corresponding to respective buffer circuits 300 in the row address buffer 3.
Each counter 500 outputs an address signal of the same bit as the external address signal (any one of Aa- Ac) to be supplied to the address input pad (any one of 10a-10c) connected to the corresponding buffer circuit 300. As a result, a row address signal of a plurality of bits designating any one row of the memory cells in each memory cell array block 2a or 2b is supplied to the row address buffer 3 not only from the address input pads 10a-10c but also from the internal address counter 5.
The row address buffer 3 takes the signals from the internal address counter 5 and applies the signals to the row predecoder 4 instead of the signals from the address input pads 10a-10c while the internal row address strobe signal int/RAS and the internal column address strobe signal int/CAS are both at the high level, that is, in a period in which neither data writing nor data reading is carried out to or from any memory cell MC.
Therefore, in such a period, the word line WL corresponding to the row designated by the output signal from the internal address counter 5 is activated in each of the memory cell array blocks 2a and 2b, and hence the data stored in all memory cells MC are refreshed.
The ATD circuit 7 detects the change in the internal column address signal intAcl and outputs a one shot pulse detecting signal. The circuitry which is to be controlled by the external column address signal/CAS such as column decoders 24a and 24b starts series of operations for writing or reading data in response to the detection signal.
The ATD circuit 7 is provided for controlling operation timings of circuits which are to be controlled by the external address strobe signal/CAS.
Most of such DRAMs having large capacities have various high speed operation modes so as to reduce access time. FIG. 7 is a timing chart showing timings of switching of the control signals, address signals and output data signals in the typical high speed operation modes of the DRAM.
Referring to FIG. 7, in a static column mode, the external row address strobe signal/RAS falls earlier than the external column address strobe signal/CAS (FIG. 7(a), (b)).
The external address signals Aa-Ac are set as the row address signals Row designating one row of memory cells in each of the memory cell array blocks 2a and 2b when the external row address strobe signal/RAS falls, while they are successively switched to column address signals Col-1, Col-2, . . . designating a plurality of columns of memory cells in each of the memory cell array blocks 2a and 2b while the external column address strobe signal/CAS is at the low level.
Therefore, as shown in FIG. 7(d), the internal row address signal intArw from the row address buffer 3 is fixed as a signal Row corresponding to the row of memory cells designated by the external address signals Aa-Ac at the time of the fall of the external address strobe signal/RAS.
The internal column address signal intAcl from the column address buffer 21 is successively switched to signals Col-1, Col-2, . . . successively designating the plurality of columns of the memory cells in each of the memory cell blocks 2a and 2b while the internal row address signal intArw is thus fixed, as shown in FIG. 7(e).
Therefore, in data reading, in the static column mode, data stored in the plurality of memory cells arranged in a single row designated by the external address signals Aa-Ac at the fall of the external row address strobe signal/RAS are supplied in the order of the data stored in the memory cell of the column designated by the signal Col-1, the data stored in the memory cell of the column designated by the signal Col-2, . . . as the output data Dout (FIG. 7(f)) of the DRAM, through the corresponding one of the sense amplifier.multidot.IO line circuits 26 and 26b and through the input/output circuit 27 from the corresponding one of memory cell array blocks 2a and 2b.
When the external address signals Aa-Ac are switched to the signals designating another column, the internal column address intAcl is switched to the signal designating this another column by the operation of the column address buffer 21, and then the signals appeared on the bit line pair BL corresponding to this another column in each of the memory cell array blocks 2a and 2b are applied to the input/output circuit 27 by the operation of the column predecoder 6 and column decoders 24a and 24b.
In the fast page mode, the external row address strobe signal/RAS and the external column address strobe signal/CAS fall in the similar timing as in the static column mode. However, different from the static column mode, the external column address strobe signal/CAS rises and falls repeatedly at predetermined timings while the external row address strobe signal/RAS is at the low level, as shown by the dotted line in FIG. 7(b).
Meanwhile, external address signals Aa-Ac are set as the signal Row designating one column of memory cells in each of the memory cell array blocks 2a and 2b at the fall of the external row address strobe signal/RAS, and these signals are set as the signal designating any one column of memory cells in each of the memory cell array blocks 2a and 2b at a timing synchronized with the fall of the external column address strobe signal/CAS as shown by the dotted line in FIG. 7(c).
Therefore, the internal row address signal intArw is fixed at a signal designating the column Row designated by the external address signals Aa-Ac at the fall of the external row address strobe signal/RAS, while the internal column address signal intAcl is switched to signals Col-1, Col-2, . . . designating a plurality of columns of memory cells at a timing synchronized with the external address strobe signal/CAS while the internal row address signal intArw is fixed at such a signal, as shown by the dotted line in FIG. 7(e).
Consequently, in data reading, the data stored in the plurality of memory cells MC arranged in the same row in each of the memory cell array blocks 2a and 2b are successively supplied externally as output data Dout at a timing corresponding to the period of the external column address strobe signal/CAS (see the dotted line of FIG. 7(f)).
Generally, in the static column mode or the fast page mode, the time T.sub.AA from the switching of the external address signals Aa-Ac to the signal designating another column of the memory cell, to the switching of the output data Dout to the data stored in the memory cells of this another column is called an access time.
Therefore, if it takes longer for the internal column address signal intAcl to switch in response to the switch of the external address signals Aa-Ac, the access time T.sub.AA becomes longer.
FIG. 8 is a schematic diagram showing a general structure of each buffer circuit 210 constituting the column address buffer 21.
Referring to FIG. 8, each buffer circuit 210 constituting the column address buffer includes a P channel MOS transistor 2000 and an N channel MOS transistor 2200 connected in series between the power supply Vcc and the ground, an inverter 2400 for inverting the potential at a node N1 between transistors 2000 and 2200, a P channel MOS transistor 2100 connected between the node N1 and the power supply Vcc, and an N channel MOS transistor 2300 connected between the node N1 and the ground GND.
Transistors 2000 and 2200 form an inverter INV of an input first stage of the buffer circuit.
An output signal from the inverter 2400 is applied to the gate of the transistor 2100. A control signal .phi. is applied to the gate of the transistor 2300.
The control signal .phi. is set such that it is switched from the high level to the low level after the signals from the address input pads 10a-10c are stored in the row address buffer 3 in response to the fall of the external row address strobe signal/RAS.
When the external address signal (any of Aa-Ac) to any one of the address input pads (any of 10a-10c) is changed from high level to the low level while the control signal .phi. is at the low level, the transistors 2000 and 2200 are turned from ON to OFF in the buffer circuit 210 provided corresponding to this one address input pad, so that the potential at the node N1 is switched from the low level to the high level, and the output signal from the inverter 2400 changes from the high level to the low level, in response. When the output signal from the inverter 2400 attains low level, the transistor 2100 turns ON, and therefore even when the control signal .phi. attains to high level thereafter, the potential at the node N1 and the output signal from the inverter 2400 are fixed at the high level and the low level, respectively.
Conversely, when the external address signal to an arbitrary address input pad changes from the low level to the high level while the control signal .phi. is at the low level, the transistors 2000 and 2200 are turned OFF and ON, respectively, so that the potential at the node N1 is switched to the low level, resulting in the high level output signal from the inverter 2400 in the buffer circuit 210 provided corresponding to this address input pad. When the output signal from the inverter 2400 attains to the high level, the transistor 2100 is turned OFF, and therefore the output signals from the node N1 and the inverter 2400 are fixed at the high level and the low level, respectively, regardless of the level of the control signal .phi..
While the control signal .phi. is at the low level, in response to the switching of the external address signals Aa-Ac to the respective address input pads 10a-10c, the output levels of the buffer circuits 210 provided corresponding to the address input pads are switched. Namely, after the row address signal is taken by the row address buffer 3, the signals Aa-Ac of the respective bits constituting the column address signal are taken in the corresponding buffer circuits 210.
Generally, in each buffer circuit 210, the inverter 2400 is a CMOS type inverter similar to that of the inverter INV of the input first stage.
Generally, the relation (transmission characteristic) of the input potential level and the output potential level of the inverter INV is unified according to a standard specification.
More specifically, the output transition point of the inverter INV, that is, the value of the input potential to the inverter INV at which the output logic level of the inverter INV changes, is set at an intermediate potential between the range of the potential to be regarded as high level and the range of the potential to be regarded as the low level.
For example, in a DRAM, the minimum value of the potential range to be regarded as the high level and the maximum value of the potential range to be regarded as the low level are 2.4 V and 0.8 V, respectively, which values are determined in accordance with a standard. Therefore, the transition point (threshold value) of the output potential of the inverter INV is set at about 1.6 V.
Namely, in each buffer circuit 210, when the potential of the corresponding address input pad exceeds 1.6 V, the inverter INV outputs a low level potential, and when the potential of the corresponding address input pad becomes lower than 1.6 V, the inverter INV outputs a high level potential.
The threshold voltages and the like of the transistors 2000 and 2200 are set so that the inverter INV has such transmission characteristics.
Generally, in such a DRAM having the block divided structure, the row address buffer 3 and the column address buffer 21 are arranged between the memory cell array blocks 2a and 2b. When the memory cell array is divided into two blocks 2a and 2b, the column address buffer 21 and the row address buffer 3 are arranged between one memory cell array block 2a and the other memory cell array block 2b, that is, the central portion of the DRAM chip 1, as shown in FIG. 6.
As described above, in the conventional DRAM, the data of each of the bits constituting the row address and the data of each bit constituting the column address are input to decoders through corresponding buffer circuits. Therefore, the magnitude of the capacitance and resistance of the interconnection provided between each address input pad and the corresponding buffer circuit much influence the time necessary for transmission of the external address signal to the decoders.
For example, referring to FIG. 6, the buffer circuits 210 constituting the column address buffer 21 are connected to the corresponding address input pads 10a-10c by interconnection layers La-Lc formed on the chip 1, respectively.
The address input pads 10a-10c are provided near the outer side of the DRAM chip 1 in order to take external signals. The column address buffer 21 is provided at the central portion of the DRAM chip 1.
Therefore, the interconnection layers La-Lc connecting the address input pads 10a-10c to the corresponding buffer circuits 210 have the length corresponding to the length of one side of the DRAM chip.
Since DRAMs have come to have larger capacitances recently, the size of the DRAM chip 1 becomes larger as compared with the prior art. Therefore, the length of one side of the DRAM chip 1 is also made longer than the prior art. Consequently, the length of the interconnection layers La-Lc becomes longer.
The resistance and capacitance of the interconnection layer increase in proportion to the length. Therefore, in a recent DRAM1 having large storage capacity, the resistance and capacitance of the interconnection layers La-Lc connecting the address input pads 10a-10c with the column address buffer 21 are considerably large.
As the resistance and capacitance of the interconnection layers La-Lc become larger, the time necessary for the internal column address signal intAcl from the column address buffer 21 to change in response to the change of the external address signal Aa-Ac becomes longer.
This phenomenon will be described in detail with reference to FIGS. 8 and 9.
Assume that an external address signal Aa supplied to the address input pad 10a changes from the high level to the low level as shown in FIG. 9(a).
In such a case, for the output signal of the buffer circuit 210 provided corresponding to the address input pad 10a to be switched immediately in response to the switching of such external address signal Aa, it is necessary that the transistors 2000 and 2200 in the buffer circuit 210 (see FIG. 8) are switched to ON and OFF, respectively, at high speed.
However, if the interconnection layer La has large capacitance and large resistance, it takes long to discharge the interconnection layer in response to the switching of the external address signal Aa. Therefore, the potentials at the gates (input ends of the inverter INV) of the transistors 2000 and 2200 do not immediately lower even if the potential of the address input pad 10a (FIG. 9(a)) falls, as shown in FIG. 9(b), but the potential reaches the low level potential V.sub.IL considerably long after the external address signal Aa has attained the low level. Namely, the potential at the input end of the buffer circuit 210 has a waveform which is considerably moderate than the waveform of the external address signal Aa.
Therefore, the time .tau.1 necessary for the potential at the input end of the buffer circuit 210 to be regarded as the low level (not higher than 1.6 V) by the inverter INV of the input first stage becomes longer. Therefore, as shown in FIG. 9(c), the output signal from the inverter INV gradually increases in response to the lowering of the signal at the input end of the inverter INV and it reaches the high level potential V.sub.IH considerably long time after the fall of the external address signal Aa.
Consequently, the time .tau.2 necessary for the output signal from the inverter INV to attain the range (not lower than 1.6 V) to be regarded as the high level by the inverter 2400 also becomes longer. Therefore, as shown in FIG. 9(d), the output signal from the inverter 2400, that is, the internal column address signal intAcl gradually lowers in response to the rise of the output signal of the inverter INV and it reaches the ground potential Vss corresponding to the low level considerably long time after the fall of the external address signal Aa.
Assume that the external address signal Aa is switched from the low level to the high level as shown in FIG. 9(a).
In that case, for the internal address signal intAcl to be immediately switched in response to the switching of the external address signal Aa, it is necessary that the output signal of the inverter INV is immediately switched to the low level in the buffer circuit 210 provided corresponding to the address input pad 10a.
However, if the interconnection layer La has large capacitance and large resistance, it takes long to charge this interconnection layer in response to the switching of the external address signal Aa. Therefore, the potential at the input end of the inverter INV shows a waveform which is considerably moderate the than the external address signal Aa as shown in FIG. 9(a), and hence it takes long time .tau.3 for the potential to reach the range which is regarded as high level by the inverter INV.
Therefore, as shown in FIG. 9(c), the output signal from the inverter INV gradually lowers in response to the rise of the potential at the input end thereof and it reaches the low level potential V.sub.IL considerably long time after the rise of the external address signal Aa.
Consequently, since the time .tau.4 necessary for the output signal from the inverter INV to reach the range regarded as the low level by the inverter 2400 becomes longer, and the output signal from the inverter 2400 slowly rises in response to the lowering of the output signal from the inverter INV and reaches the supply potential Vcc corresponding to the high level, considerably long time after the rise of the external address signal Aa, as shown in FIG. 9(d).
As described above, if the interconnection layer La has large resistance and large capacitance, the time T1 necessary for the output signal of the buffer circuit 210 provided corresponding to the address input pad 10a to completely reach the low level and the time T2 necessary for the output signal of the buffer circuit 210 provided corresponding to the address input pad 10a to completely reach the high level, that is, the time necessary for the output level of the buffer circuit 210 provided corresponding to the address pad 10a to be switched in response to the change of the level of the external address signal Aa becomes longer.
Similarly, the increase of the resistance and of the capacitance of the interconnection layers Lb and Lc increase time necessary for the changes in the levels of the corresponding external address signals Ab and Ac to reach the corresponding internal address signals.
If it takes long to transmit the change of the external address signals Aa-Ac to the internal address signal intAcl, the time from the switching of the external address signal to electrical connection of one bit line pair BL provided corresponding to the column designated by the switched external address signal to the sense amplifier IO line circuit 26a or 26b by the operation of the column predecoder 6, column decoder 24a and the ATD circuit 7 in each of the memory cell array blocks 2a and 2b takes longer.
Therefore, in the fast page mode or a static column mode, for example, in the period after the external address signals Aa-Ac are taken as row addresses in the row address buffer 3 in response to the fall of the external row address strobe signal/RAS, the time (the time for data reading) necessary for the output data Dout from the input/output circuit 27 to be switched from the data stored in the memory cell MC arranged at one column to the data stored in the column of the memory cells MC arranged in another column in each of the memory cell array blocks 2a and 2b in response to the switching of the external address signals Aa-Ac indicating a certain column of memory cells to another column of memory cells, and the time (time for data writing) necessary for the external data Din to be written to one memory cell MC arranged in this another column in each of the memory cell array blocks 2a and 2b becomes longer in each of the memory cell array blocks 2a and 2b.
As described above, if the interconnection layer connecting the address input pad and the buffer circuit for taking the external address signal applied to this address input pad to apply the same to the decoder has large resistance and large capacitance, the waveform of the potential at the input end of the buffer circuit becomes moderate, resulting in longer access time of the DRAM.
Such moderate signal waveform of the input end of the buffer circuit caused by the increased resistance and capacitance of the interconnection layer also affects power consumption of the buffer circuit.
Referring to FIGS. 8 and 9, assume that the signal at the input end of the inverter INV slowly changes to the low level and to the high level in response to the fall and rise of the external address signal Aa, respectively, as shown in FIG. 9(b) in buffer circuit 210.
In such a case, both transistors 2000 and 2200 in the inverter INV are kept ON longer in the period from the potential at the input end of the inverter INV changes from the high level potential V.sub.IH to the low level potential V.sub.IL and in the period in which it changes from the low level potential V.sub.IL to the high level potential V.sub.IH.
The threshold voltage of a MOS transistor is generally 0.8 V, for example, which is considerably smaller than the difference voltage between the high level potential V.sub.IH and the low level potential V.sub.IL.
Therefore, the P channel transistor 2000 constituting the inverter INV is turned ON if the gate potential thereof is lower than or equal to a potential Vthp which is lower than the high level potential V.sub.IH by the threshold voltage Vthp, and the N channel transistor 2200 constituting the inverter INV is turned ON if the gate potential thereof is higher than or equal to a potential Vthn which is higher than the low level potential V.sub.IL by the threshold voltage.
Therefore, in the period in which the potential at the input end of the inverter INV is in the range from Vthn-Vthp, the transistors 2000 and 2200 are both ON. If the speed of lowering and increasing the potential at the input end at the inverter INV become slower, the period in which the gate potentials of the transistors 2000 and 2200 are in such a range Vthn-Vthp becomes longer. Namely, the period in which transistors 2000 and 2200 are both ON becomes longer.
In the period in which transistors 2000 and 2200 are both ON, there is generated a current flowing from the power supply Vcc to the ground through the transistors 2000 and 2200, that is, a through current. Therefore, if such period in which the transistors 2000 and 2200 are both ON becomes longer, the power consumption in the buffer circuit 210 is increased because of the increased through current in the inverter INV.
As described above, the increase of the resistance and capacitance of the interconnecting layer connecting the address input pad to the buffer circuit for buffering the external address signals cause increased power consumption of the buffer circuit, and as a result, it prevents reduction of power consumption in the DRAM.
As the storage capacity of the DRAMs has come to be larger and larger, the length of one side of the DRAM chip 1 has come to be longer. Therefore, the above described problem derived from the increased resistance and capacitance of the interconnection layers La-Lc become more serious in the recent DRAMs having large storage capacity.